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CD74HCT112 - Dual J-K Flip-Flop

Download the CD74HCT112 datasheet PDF. This datasheet also covers the CD74HC112 variant, as both devices belong to the same dual j-k flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Set and Reset Complementary Outputs Buffered Inputs TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Ran

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Note: The manufacturer provides a single datasheet file (CD74HC112-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
CD74HCT11 High-Speed CMOS Logic Triple 3-Input AND Gate
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Full PDF Text Transcription

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Data sheet acquired from Harris Semiconductor SCHS141H March 1998 - Revised October 2003 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger [ /Title (CD74 HC112 , CD74 HCT11 2) /Subject (Dual J-K FlipFlop with Set and Reset Nega- Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Set and Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . .
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